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Home/ Questions/Q 6784339
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Editorial Team
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Editorial Team
Asked: May 26, 20262026-05-26T16:58:47+00:00 2026-05-26T16:58:47+00:00

I have a function using inline assembly: vec8w x86_sse_ldvwu(const vec8w* m) { vec8w rd;

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I have a function using inline assembly:

  vec8w x86_sse_ldvwu(const vec8w* m) { 
     vec8w rd; 
     asm("movdqu %[m],%[rd]" : [rd] "=x" (rd) : [m] "xm" (*m)); 
     return rd; 
  } 

It gets compiled to the following assembly code:

  sub    $0x1c,%esp
  mov    0x24(%esp),%eax
  movdqa (%eax),%xmm0 
  movdqu %xmm0,%xmm0
  movdqa %xmm0,(%esp)
  movdqa (%esp),%xmm0
  add    $0x1c,%esp
  ret 

The code isn’t terribly efficient, but that isn’t my concern. As you can see the inline assembler inserts a movdqa instruction copying from the address in %eax to xmm0. The problem is that the pointer vec8w* m is not 128 bytes aligned, so I get a seg fault when movdqa is being executed.
My question is whether there is a way to instruct the inline assembler to use movdqu instead of movdqa (that it uses by default)? I tried to look for a workaround using SSE intrinsic functions for g++, but somehow I cannot find movdqu in xmmintrin.h file (where it should be declared, I suppose).
Unfortunately, I cannot modify the code so that the function is always called for an aligned argument m.

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1 Answer

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  1. Editorial Team
    Editorial Team
    2026-05-26T16:58:47+00:00Added an answer on May 26, 2026 at 4:58 pm

    The intrinsic that you are looking for is _mm_loadu_si128. It is defined in emmintrin.h. Which is SSE2. The xmmintrin.h header contains only SSE(1) instructions.

    http://software.intel.com/sites/products/documentation/studio/composer/en-us/2011/compiler_c/intref_cls/common/intref_sse2_int_load.htm

    _mm_loadu_si128 will emit the movdqu instruction which you are looking for. It seems that’s exactly what you are trying to accomplish with your inline assembly function. (a misaligned load)

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