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Editorial Team
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Editorial Team
Asked: May 15, 20262026-05-15T20:22:35+00:00 2026-05-15T20:22:35+00:00

I have a makefile structured something like this: all : compile executable clean :

  • 0

I have a makefile structured something like this:

all : 
    compile executable

clean :
    rm -f *.o $(EXEC)

I realized that I was consistently running “make clean” followed by “clear” in my terminal before running “make all”. I like to have a clean terminal before I try and sift through nasty C++ compilation errors. So I tried to add a 3rd target:

fresh :
    rm -f *.o $(EXEC)
    clear
    make all

This works, however this runs a second instance of make (I believe). Is there a right way to get the same functionality without running a 2nd instance of make?

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  1. Editorial Team
    Editorial Team
    2026-05-15T20:22:37+00:00Added an answer on May 15, 2026 at 8:22 pm

    Actually you are right: it runs another instance of make.
    A possible solution would be:

    .PHONY : clearscr fresh clean all
    
    all :
        compile executable
    
    clean :
        rm -f *.o $(EXEC)
    
    fresh : clean clearscr all
    
    clearscr:
        clear
    

    By calling make fresh you get first the clean target, then the clearscreen which runs clear and finally all which does the job.

    EDIT Aug 4

    What happens in the case of parallel builds with make’s -j option?
    There’s a way of fixing the order. From the make manual, section 4.2:

    Occasionally, however, you have a situation where you want to impose a specific ordering on the rules to be invoked without forcing the target to be updated if one of those rules is executed. In that case, you want to define order-only prerequisites. Order-only prerequisites can be specified by placing a pipe symbol (|) in the prerequisites list: any prerequisites to the left of the pipe symbol are normal; any prerequisites to the right are order-only: targets : normal-prerequisites | order-only-prerequisites

    The normal prerequisites section may of course be empty. Also, you may still declare multiple lines of prerequisites for the same target: they are appended appropriately. Note that if you declare the same file to be both a normal and an order-only prerequisite, the normal prerequisite takes precedence (since they are a strict superset of the behavior of an order-only prerequisite).

    Hence the makefile becomes

    .PHONY : clearscr fresh clean all
    
    all :
        compile executable
    
    clean :
        rm -f *.o $(EXEC)
    
    fresh : | clean clearscr all
    
    clearscr:
        clear
    

    EDIT Dec 5

    It is not a big deal to run more than one makefile instance since each command inside the task will be a sub-shell anyways. But you can have reusable methods using the call function.

    log_success = (echo "\x1B[32m>> $1\x1B[39m")
    log_error = (>&2 echo "\x1B[31m>> $1\x1B[39m" && exit 1)
    
    install:
      @[ "$(AWS_PROFILE)" ] || $(call log_error, "AWS_PROFILE not set!")
      command1  # this line will be a subshell
      command2  # this line will be another subshell
      @command3  # Use `@` to hide the command line
      $(call log_error, "It works, yey!")
    
    uninstall:
      @[ "$(AWS_PROFILE)" ] || $(call log_error, "AWS_PROFILE not set!")
      ....
      $(call log_error, "Nuked!")
    
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