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I have a microprocessor with the card’s chip select (CS) line tied to a ‘frame’ signal automatically driven by the SPI (SSP) circuit. This causes CS to go high between each byte.
The MMC/SD specs require that CS be held low in order to enter SPI mode. Does it need to be held low the entire time, or only when transmitting each byte of CMD0?
At the sdcard.org site, I found various PDF specifications for SDIO. None of these seem to have an explicit timing statement which clarifies this. However, this statement does occur:
from page 88 of SD Host Controller Simplified Specification Version 2.00. (“Pin 1” is Chip Select (
CS))Given that sentence, an SD card manufacturer would be justified in requiring that you assert
CSthrough the entireD0..D15bits being sent. In other words, I think you cannot use the SPI frame signal and will need a GPIO pin or similar.