Question

I have a piece of Verilog code worked upon by a programmer no longer in the company I work for. An extract is given below:

parameter mstrobe = 10;
.
.
.
assign #(mstrobe) sclk=iclk;

(sclk is a wire, iclk is assigned the value of system clock)

I also have a separate Perl script for carrying out some manipulations on existing Verilog files. This script chokes in parsing #(mstrobe) because mstrobe is enclosed within parenthesis. While I can fix that easily, what I want to know is whether there is a fundamental difference between the assign statement above and

assign #mstrobe sclk=iclk;

I want to be sure whether the two statements are equivalent, or perhaps whether there are any differences in syntax in this regard between Verilog versions (Verilog-2001, Verilog-2005, SystemVerilog).

Answer 1

In your simple case, the parentheses are optional; both cases are valid syntax, regardless of Verilog version.

The parentheses would be required if you had a more complex expression, such as:

assign #(mstrobe/2) sclk=iclk;

On a side note, since you are parsing Verilog using Perl, are you aware of Verilog-Perl?