Question

I have a source file test.c and its header test.h, a file main.c and the makefile.
I want to set up my makefile so that it (1) compiles test.c to build an executable test.o,
and (2) compiles test.c to print the assembly code to test.s using -S flag.

I have tried to set up the makefile as I thought would be correct, but this of course doesn’t actually run the last test.s line.

FLAGS = -c -Wall
CC = gcc
ASM = -S

all : optimize
optimize: main.o test.o
    $(CC) main.o test.o -o optimize
main.o: main.c test.h
    $(CC) $(FLAGS) main.c
test.o: test.h test.c
    $(CC) $(FLAGS) test.c
test.s: test.h test.c
    $(CC) $(ASM) -Wall test.c

Can anyone tell me how I should have structured this differently, to create both test.s and test.o?

I tried to change the optimize: line and the following one to:

optimize: main.o test.o test.s
    $(CC) main.o test.o test.s -o optimize

but the linker gave an error multiple definition of 'test'.

Answer 1

Simply add test.s to the line that starts with optimize:.

What this does is add the rule test.s to the dependencies of the optimize line.

You could also add it to the all line, as suggested by Vaughn Cato.

It’s important to know that there is a difference between the rule test.s and the file test.s

You can put anything you want as the name of the rule, but by convention you normally just use the filename.

Here’s an example Makefile that will do what you want. I put the dep under all so you can just make asm and I also changed the rule name to asm for clarity.

FLAGS = -c -Wall
CC = gcc
ASM = -S

all : optimize asm
optimize: main.o test.o
    $(CC) main.o test.o -o optimize
main.o: main.c test.h
    $(CC) $(FLAGS) main.c
test.o: test.h test.c
    $(CC) $(FLAGS) test.c
asm: test.h test.c
    $(CC) $(ASM) -Wall test.c -o test.s

Finally, because you seem a bit shaky on how Makefiles work, (I don’t blame you honestly), I suggest reading this tutorial: http://mrbook.org/tutorials/make/