I have a top level Verilog module that instantiates a VHDL block with a few outputs that are records.
Is there a good way to access these records from my Verilog top, or am I better off just breaking the records apart?
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I have a top level Verilog module that instantiates a VHDL block with a few outputs that are records.
Is there a good way to access these records from my Verilog top, or am I better off just breaking the records apart?
You can (with caveats). Create a “struct” of the same type as the “record”. These two will map 1:1 as long as you do not reorder the connections. Caveat being if your tool actually supports it.