Question

I have read the ARM document about Cortex-M3 (or M0) and it say it can be used as level sensetive or pulse (edge) interrupt within the NVIC controller. The problem that it rather vague on how to do this, if this is done by software.

I fails to see any kind of register within the NVIC or such that control the type of the interrupt (to select edge or level by adjusting the register bits). So something must be done by software within handler but again it vague in this field.

I like to hear anyone having a way to make it edge or level trigger interrupt by software.

Please demonstrate within the handler code (if this control it) that the make it detect for level or pulse.

If this is level detect, I can hold interrupt active and disable by the handler, until restore by external code for which it re-excute the interrupt. This is what I’m trying to do, but it will not work if this is pulse detect type.

Thx

Answer 1

A document that describes how the Cortex-M3 NIVC handles level or edge (pulse) triggered interrupts can be found here:

• Cortex-M3 Devices Generic User Guide, 4.2.9. Level-sensitive and pulse interrupts

This may well be the document you refer to in your question. Joseph Yiu’s book, “The Definitive Guide to the ARM Cortex-M3” also has a pretty good description.

There is no particular configuration of the NVIC for these two interrupt signal types – it handles either kind. Essentially, when an interrupt is asserted (whterh level-based or edge triggered) the NVIC latches that status in the SETPENDx register. When the ISR for that interrupt is vectored to, the corresponding bit in the ACTIVEx register will be set and the bit in the SETPENDx register will be cleared.

While the interrupt is active, if the interrupt line transitions from inactive to active, the pending bit will be turned on again, and upon return from the current active ISR instance, the interrupt will be handled again. This handles the edge triggered interrupt case.

Also, when the ISR returns (and the NVIC clears the ‘active’ bit), the NIVC will reexamine the state of the interrupt line – if it’s still asserted it will set the pending bit again (even if there hasn’t been a a transition from inactive to active). This handles the case where an interrupt is level triggered, and the ISR didn’t manage to cause the interrupt to be de-asserted (maybe a second device on a shared IRQ line asserted its interrupt at just the critical moment so there was no time when the interrupt line was inactive).

If this is level detect, I can hold interrupt active and disable by the handler, until restore by external code for which it re-execute the interrupt.

I’m not sure I really understand what you’re after here, but I think that you might be able to do what you want using the NVIC’s SETENAx and CLRENAx registers to enable/disable the interrupt. These work independently of the pending bits, so an interrupt can be pending (or become pending) even if the interrupt is disabled. So you can hold off handling an interrupt for as long as you want.

If that’s not quite enough, also note that you can cause an interrupt to pend via software by simply setting the pending bit in the corresponding SETPENDx register – the CPU will vector to the ISR just as if a hardware interrupt were asserted (assuming the interrupt is enabled in the SETENAx register). you can also use the “Software Trigger Interrupt Register” (STIR) to trigger an interrupt by software.