Question

I have several C and C++ projects that all follow a basic structure I’ve been using for a while now. My source files go in src/*.c, intermediate files in obj/*.[do], and the actual executable in the top level directory.

My makefiles follow roughly this template:

# The final executable
TARGET := something
# Source files (without src/)
INPUTS := foo.c bar.c baz.c

# OBJECTS will contain: obj/foo.o obj/bar.o obj/baz.o
OBJECTS := $(INPUTS:%.cpp=obj/%.o)
# DEPFILES will contain: obj/foo.d obj/bar.d obj/baz.d
DEPFILES := $(OBJECTS:%.o=%.d)

all: $(TARGET)

obj/%.o: src/%.cpp
    $(CC) $(CFLAGS) -c -o $@ $<

obj/%.d: src/%.cpp
    $(CC) $(CFLAGS) -M -MF $@ -MT $(@:%.d=%.o) $<

$(TARGET): $(OBJECTS)
    $(LD) $(LDFLAGS) -o $@ $(OBJECTS)

.PHONY: clean
clean:
    -rm -f $(OBJECTS) $(DEPFILES) $(RPOFILES) $(TARGET)

-include $(DEPFILES)

Now I’m at the point where I’m packaging this for a Debian system. I’m using debuild to build the Debian source package, and pbuilder to build the binary package. The debuild step only has to execute the clean target, but even this causes the dependency files to be generated and included.

In short, my question is really: Can I somehow prevent make from generating dependencies when all I want is to run the clean target?

Answer 1

The solution is easy, don’t -include generated files under clean:

ifneq ($(MAKECMDGOALS),clean)
    -include $(DEPFILES)
endif