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I have some self-testing code for my SystemVerilog component and I want to ensure that my tests cover everything, especially the failure cases in my classes. All I need is line/branch coverage, just like what is normally used for other object oriented languages such as Java.
I tried using VCS (version 2012.06) coverage, and I found it only has a limited support for SystemVerilog, and does not support any coverage for SystemVerilog classes. Is there any simulator or tool that has this support?
2012/08/25
Until further notice, the answer is:
No, there is no tool/simulator that supports line coverage for SystemVerilog classes.