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Home/ Questions/Q 4578896
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Editorial Team
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Editorial Team
Asked: May 21, 20262026-05-21T20:33:58+00:00 2026-05-21T20:33:58+00:00

I have the following code which is a part of my digital clock: library

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I have the following code which is a part of my digital clock:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

-- Seconds counter
entity SecCounter is
    port( 
            s_enable: in std_logic;
            s_load: in std_logic; -- When high, sets this counter to the value in the     data inputs
            s_clk: in std_logic; -- Clock
            s_input: in std_logic_vector(5 downto 0); -- Data inputs
            s_output: out std_logic_vector(5 downto 0); --Outputs
            s_wrap: out std_logic
        );
    end SecCounter;

architecture imp of SecCounter is
    -- Intermediate signal to mainpulate the seconds as integer
    signal sec: integer range 0 to 60 := 22;

    begin
        s_output <= std_logic_vector(to_unsigned(sec,6)); -- Assign the input to the binary     value of sec

        process(s_clk, s_load, s_enable) -- If clk, enable, or load is changed
        begin
            s_wrap <= '0'; -- Clear the wrap

            if (s_enable = '0' and s_load = '1') then -- Set the clock
                sec <= to_integer(unsigned(s_input));
            elsif (s_enable = '1' and rising_edge(s_clk)) then -- Increment the counter
                sec <= sec + 1;
            end if;

            if sec = 60 then -- Restart counter and toggle the next counter
                sec <= 0;
                s_wrap <= '1';
            end if;
        end process;
end imp;

s_wrap acts as an enable to the next counter. What I’m trying to do is that if this counter equals 60 I want to enable the next counter for a single clock edge. I’m trying to do this through setting s_wrap to true and then to false in the next clock edge; however, it doesn’t change. Is there a way to make is_wrap stateless? IF not, how can I solve this problem?

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  1. Editorial Team
    Editorial Team
    2026-05-21T20:33:59+00:00Added an answer on May 21, 2026 at 8:33 pm

    You are assigning values to sec outside of the rising_edge(clk) clause. And you are not assigning anything to sec if s_enable=0 and s_load=0. Either of those facts make sec an asynchronous signal. If you fix both then the described problem should go away.

    And Oli Charlesworth has a good point about checking for 59 rather than 60. Then you do not have to artificially include the non-existent 60 in your range either. And initializing sec to a value is not meaningful. You should initialize it in your reset clause.

    You may have other problems since you are reading s_enable, s_load and s_input asynchronously. That is normally done only for the reset signal.

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