Question

I have the following hypthetical Makefile:

all: SOURCE = $(wildcard src/*.cpp)
unity: SOURCE = $(wildcard unity/*.cpp)

OBJECTS = $(SOURCE:.cpp=.o)

all: prog

unity: prog

prog: $(OBJECTS)
    $(CXX) $(OBJECTS) -o prog

I need to compile with different source files / objects based on the initial target. It appears to me that variable expansion happens much earlier on the dependencies than in the target body as the above compiler command is called just fine with the right filenames, but the $OBJECTS in the prog dependency is still empty so none of the objects have been built.

The unity folder contains a combined source file with all other source files included for doing unity builds. This unity file is generated by the makefile, but this is left out and may in fact be multiple unity object files.

Is my design a lost cause? Am I going to have to resort to recursive make to achieve this?

Answer 1

You can’t do that. Because in general, there may be multiple targets which need to be built. On the commandline, or as an intermediate goal.
So setting the variable would be ambigous. Becasue of this, the values of target specific variables “are only available within the context of a target’s command script (and in other target-specific assignments).” (see File: make.info, Node: Target-specific)

But you can inspect the MAKECMDGOALS variable.