Question

I have this makefile:

SHELL=/bin/zsh
COMPILER=g++ -g
COMPILERSO=g++ -a +a1 -b
LIBDIR=/Users/romeovs/Desktop/rootex
CFLAGS=$(root-config --cflags)
LIBS=$(root-config --libs) -lPhysics -lThread -lMinuit -lHtml -lVMC -lEG -lGeom
ROOT=/usr/local/bin/root -b -q

.SUFFIXES=.C .o

WriteTree : WriteTree.C Event.o Event_C.so Event.h
    ${COMPILER} WriteTree.C -o  $@ Event.o Event_C.so ${CFLAGS} ${LIBS}
Event_C.so : BuildLibDico.C
     ${ROOT} BuildLibDico.C
Event.o : Event.C Event.h
    ${COMPILER} -c ${CFLAGS} Event.C 

When I run in make Event.o int the command line, one would expect make would run:

${COMPILER} -c ${CFLAGS} -o Event.o Event.C

which should expand to

g++ -g -c $(root-config --cflags) -o Event.o Event.C

which in turn should have $(root-config --cflags) expanded.

Yet when I do this make hails:

g++     -c -o Event.o Event.C

(note the extra space between g++ and -c). This in turn causes compilation errors of course.

It seems as if the expansion doesn’t work properly. Running:

g++ -c $(root-config --cflags) -o Event.o Event.C 

does work though.

What can I do to fix this?

---

EDIT

One part of the problem is fixed by Gilles answer.

Another part of the problem was that make didn’t actually look food a makefile in the directory (it’s called WriteTree.make), and was running the basic g++ command.

This can be fixed by using make -f WriteTree.make Event.o, yet I don’t know if it’s good make behavior (I would really like it to look for itself for makefiles, not only makefile but every *.make).

Answer 1

CFLAGS=$(root-config --cflags) sets CFLAGS to the value of the make variable with the bizarre name root-config --cflags. Since you have no such variable, the expansion is empty. Note that make accepts either ${variable_name} or $(variable_name), and if the character following the $ isn’t an opening parenthesis or brace then it’s used as a variable name (even e.g. $foo expands to the value of the variable named f followed by the two characters oo).

You need to double the dollar sign: $$ expands to a single $, and then you’ll have a shell snippet.

CFLAGS = $$(root-config --cflags)
LIBS = $$(root-config --libs) -lPhysics -lThread -lMinuit -lHtml -lVMC -lEG -lGeom

Another error is that .SUFFIXES = .C .o should have a colon instead of the equal sign: .SUFFIXES: .C .o. This doesn’t matter here since you have no implicit rule.

Finally, make looks for Makefile (or makefile with some implementations; GNU make first tries GNUmakefile). Make only reads a single makefile in any case (not counting files reached through include directives). If you want to use a different makefile, you need to specify it explicitly on the command line, with the -f option. If you want to split your rules into several makesfiles, write a master makefile that includes them all; note that the makefiles will share a single namespace for targets and variables. In GNU make, you can include all files matched by a wildcard pattern:

include $(wildcard *.make)

Note that the file names are relative to the current directory that you invoked make from. If you want to look for files in the same directory as the makefile, you need to indicate it explicitly:

include $(wildcard $(dirname $(lastword $(MAKEFILE_LIST)))/*.make)