Question

I have this VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity addDecoder is
port(addrInput : in real; 
  ROM_sel_n, RAM_sel_n, PIO_sel_n, SIO_sel_n, INT_sel_n : out bit);
end addDecoder;

architecture Behavioral of addDecoder is

begin
AddSelect : process(addrInput) is
begin   
    if(addrInput <= X'3FFF') then
        ROM_sel_n <= '1';
    elsif(addrInput > X'3FFF' and addrInput <= X'5FFF') then
        RAM_sel_n <= '1';
    elsif(addrInput > X'5FFF' and addrInput <= X'8FFF') then
        PIO_sel_n <= '1';
    elsif(addrInput > X'8FFF' and addrInput <= X'9FFF') then
        SIO_sel_n <= '1';
    elsif(addrInput > X'9FFF' and addrInput <= X'FFFF') then
        INT_sel_n <= '1';
end process AddSelect;
end Behavioral;

What is wrong with it. I’m getting an error with the comparing of the hexadecimal values. Am I not doing this correctly? The error is this: parse error, unexpected INTEGER_LITERAL, expecting OPENPAR or IDENTIFIER

Answer 1

As Philippe already said, don’t use std_logic_arith/unsigned. Use numeric_std. I’ve written about why….

If you want to continue to make comparisons with vectors (as well as using " rather than ' around the values) you should make your addrInput an unsigned vector.

if addrInput < X"1FFF" then

Alternatively make it a natural and compare against integer values:

if addrInput < 8191 then

Also, as you are using elsif, you could simplify your statements thus:

if addrInput <= X"3FFF" then
    ROM_sel_n <= '1';
elsif addrInput <= X"5FFF" then
    RAM_sel_n <= '1';
-- etc

Finally, drop the ()s around your if conditions, it makes you look like a C-programmer 🙂