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I have to deal with a lot of multithreaded programming at work. Specifically, I want to know how the ARM memory model differs from IA64. Both are very weak models, but are there any specific differences that I should know about? I’m familiar with ia64, not with arm.
I have the same question, and while I haven’t completely found the answer, this paper might be useful: Reasoning about the ARM weakly consistent memory model
In the Further Work section, it seems to imply that no one (even at ARM, since they wrote the paper) has answered the question formally:
Update: Also look at Memory Barriers: a Hardware View for Software Hackers by Paul McKenney. It discusses the types of memory access reordering that various processors do and what instructions are available to fence the accesses. In particular, note Table 5 on page 16 that summarizes the allowed reorderings for each architecture. ARMv7, IA64, POWER, and SPARC RMO all share the same characteristics, namely, that without a barrier, anything except dependent loads can be reordered.