Question

I have to do the verification of DPRAM.

Each test case is written in different file named test1.v,test2.v etc.

I want to write a script(unix) such that when I type run test1.v then only that test case will run.

Note :- test1.v contents only task which includes read assert,write assert etc.

The test bench is a separate file which includes clock and component instantiation.

when run test1.v is done then it should link the test1.v task to the testbench and then output is obtained.

I have done the coding in verilog

How to do this?

Answer 1

So, as far as I can make out, your different tests, or ‘testcases’ are in files named test<n>.v. And I’ll assume that each of these testcases has a task that has the same name in all files, say run_testcase. This means that your testbench (testbench.v, say) must look something like:

module testbench();   
   ...
   `include "test.v" // <- problem is this line
   ...
   initial begin 
     // Some setup
     run_testcase();
     //
     $finish;
  end
endmodule

So your problem is the include line – a different file needs to be included depending on the testcase. I can think of two ways of solving this first one is as toolic suggested – using a symbolic link to ‘rename’ the testcase file. So an example wrapper script (run_sim1) to launch your sim might look a bit like:

#! /usr/bin/env sh
testcase=$1
ln -sf ${testcase} test.v
my_simulator testbench.v

Another way is to use a macro, and define this in the wrapper script for your simulation. Your testbench would be modified to look like:

   ...
   `include `TESTCASE
   ...

And the wrapper script (run_sim2):

#! /usr/bin/env sh
testcase=$1
my_simulator testbench.v +define+TESTCASE=\"${testcase}\"

The quotes are important here, as the verilog include directive expects them. Unfortunately, we can’t leave the quotes in the testbench because it will then look like a string to verilog, and the TESTCASE macro won’t be expanded.