Question

I have written a make file.

In the make file i have used a variable, say EXTRAFLAGS which looks like this.

EXTRAFLAGS += -D _MSC_VER
EXTRAFLAGS += -D BINARYINPUT
EXTRAFLAGS += -D ENABLEVERSION2D2

Further,
I use Compiler flags

CFLAGS = -Werror -Wall -I $(INC) $(EXTRAFLAGS)

and

mingw32-gcc $(CFLAGS) -o nameofexe  OBJ's 

I have used this makefile with out any problems. But when i disable the preprocessor definitions, by introducing ‘#’ ahead of one of the statments in EXTRAFLAGS, and i remake it, i am getting target up to date. I am unable to introduce Preprocessor Definitions in to the sensitive list.

A temporary work around i am using currently is, introduce a phony target clean and remove all the object files and re compiling every thing. But this is a waste of time. How can i better manage the current scenario?

Answer 1

Make is a tool that compiles your project new when one of your files in the project change.

E.g. when you change your .h file it recognizes the change and rebuilds all files that depend on it, and then rebuild all that depends on the new builds, …

But when you change the compiler flags and/or the defines in the makefile the project input files do not change, so the project is not rebuild.

There are three ways to achieve what you want: First issue manually a make clean after changing the makefile. Secondly to include the makefile itself in your makefile (and issue there a make clean when it changed). And finally move the defines into some project specific .h file.

Generally only the “in-a-h-file-on-its-own”-solution is the only one, that avoids building everything new, as the others are not aware of which source files actually have a reference to the changed defines.