Question

i need to build 4 targets from the same set of source files.
The only thing that changes are a couple of symbol definitios at compile time (-D DEBUG_OUTPUT, -D TIME_OUTPUT)

how can I accomplish that in a GNU makefile?

I thought of running a gnu make ‘for loop’ and re-declare the $(SYMBOLS) and $(TARGETNAME) each time, then run make $(TARGETNAME) from within the for loop.

Is that possible?
Is there a better way (preferrably using gnu make and not automake, or some other variant)

Thank you,
nass

Answer 1

How about this:

foo: DEBUG_OUTPUT=yes
foo: TIME_OUTPUT=2

bar: DEBUG_OUTPUT=no
bar: TIME_OUTPUT=3

baz: DEBUG_OUTPUT=maybe
baz: TIME_OUTPUT=5

qux: DEBUG_OUTPUT=dunno
qux: TIME_OUTPUT=7

TARGETS = foo bar baz qux

all: $(TARGETS)

$(TARGETS): $(SOURCE_FILES)
    @echo compile $^ into $@ using $(DEBUG_OUTPUT) and $(TIME_OUTPUT)