I need to export a user-defined GNU make function (i.e. a recursively expanded makefile variable) to a sub-make. However, make seems to expand all such variables into simply expanded variables, which makes them useless.
Here is an example:
Contents of “parent.make”:
export myfunc = my arg is $1
$(info parent testing myfunc: $(call myfunc,parent))
all: ; $(MAKE) -f child.make
Contents of “child.make”:
$(info child testing myfunc: $(call myfunc,child))
nullrule: ; @true
Running “make -f parent.make” produces the following output:
parent testing myfunc: my arg is parent
make -f child.make
child testing myfunc: my arg is
Parent exports myfunc as a simple expanded variable containing “my arg is” to the sub-make, making it useless as a function.
I’m not sure if this will satisfy your requirements, but here goes:
parent.make:
child.make:
EDIT:
All right, how about this:
child.make:
EDIT:
Not so fast. Take a look at this:
parent.make:
child.make:
grandchild.make:
This works with no modification at all to
child.makeorgrandchild.make. It does require thatparent.makecallmyfunc_baserather thanmyfunc; if that’s a problem there’s a way around it, maybe more than one.One possibility, we move the definition up into whatever calls
parent, where it won’t actually be called at all:grandparent.make:
parent.make:
I realize this might not be workable, since the definition of
myfuncmight require other things defined inparent.make. See if this will suit your situation; there may be another way…