Question

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

Answer 1

Typically you’d use the IEEE.math_real uniform function

use IEEE.math_real.all; procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real); 

But do a tiny bit a research on pseudo random number generators (PRNGs) and you’ll find many variants that are simple LFSR‘s – which look remarkably similar to CRC generators.

Here are several resources if you want to roll your own starting from existing, working PRNGs:

http://www.opencores.org/?do=project&who=systemc_rng

http://verificationguild.com/modules.php?name=Downloads&d_op=viewdownload&cid=3

Here’s a CRC VHDL code generator:

http://www.easics.be/webtools/crctool