Sign Up to our social questions and Answers Engine to ask questions, answer people’s questions, and connect with other people.
Login to our social questions & Answers Engine to ask questions answer people’s questions & connect with other people.
Lost your password? Please enter your email address. You will receive a link and will create a new password via email.
Please briefly explain why you feel this question should be reported.
Please briefly explain why you feel this answer should be reported.
Please briefly explain why you feel this user should be reported.
I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?
Thanks in advance.
If you have access to a modern simulator which supports SystemVerilog syntax, there is a
stringdata type. Strings can be concatenated and compared. Refer to the IEEE Std (1800-2009).