Question

I need to upsample(2x) my data using Verilog. I think to use three ports for input and one port for output. Input ports are filterin, reset and clock. Output port is filterout. Also I need dynamic input size. How can I realize this with Verilog.

Edit1:
My input and output datas are 16 bit long. I just need a Verilog code to do this:

If Input: 1 2 3,
Then Output: 1 0 2 0 3 0.

If Input: 1 2 3 4 5,
Then Output: 1 0 2 0 3 0 4 0 5 0.

Edit2:
I created a verilog file to solve this but it didn’t solve my problem.

US1.v file

`timescale 1ns / 1ps

module US1 (filterin,clk,filterinus);

    input [15:0] filterin;
    input clk;

    output reg [15:0] filterinus;

    integer i=0;

    always @ (posedge clk) begin
        if (i==0) begin
            filterinus <= filterin;
        end
        else begin
            filterinus <= 0;
        end
        i=~i;
    end


endmodule

I tested this code with the following Test bench:

Test.v file

`timescale 1ps/1ps
module Test;

    reg [15:0] filterin;
    reg clk;
    wire [15:0] filterinus;

    US1 uut (
        .filterin(filterin), 
        .clk(clk),
        .filterinus(filterinus)
    );

    initial begin
        clk = 1;

        filterin = 1;
        #2 filterin = 2;
        #2 filterin = 3;
        #2 filterin = 4;
        #2 filterin = 5;

        #30 $finish;
    end

    always #1 clk = ~clk;

endmodule

As is seen, my input is: 1 2 3 4 5.
My output is: 1 0 3 0 5 0 5 0 5 0…
I need to see: 1 0 2 0 3 0 4 0 5 0 0 0 0 0…

Answer 1

Problem solved. I changed filterin input period from my testbench like this:

    filterin = 1;
    #4 filterin = 2;
    #4 filterin = 3;
    #4 filterin = 4;
    #4 filterin = 5;
    #4 filterin = 0;

And I got my output: 1 0 2 0 3 0 4 0 5 0 0 0…