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Editorial Team
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Asked: 2026-05-31T16:25:18+00:00

I noticed that Verilog rounds my real number results into integer results. For example

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I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it shows the result of 17/2 as 9. What should I do? Is there anyway to define something like a: output real reg [11:0] output_value ? Or is it something that has to be done by simulator settings?

Simulation only (no synthesis). Example:
x defined as a signed input and output_value defined as output reg.

output_value = ((x >>> 1) + x) + 5;

If x=+1 then output value has to be: 13/2=6.5.

However when I simulate I see output_value = 6.

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  1. Editorial Team

    Code would help, but I suspect your not dividing reals at all. 17 and 2 are integers, and so a simple statement like that will do integer division.

    17   / 2   = 8 (not 9, always rounds towards 0)
17.0 / 2.0 = 8.5

    In your second case

    output_value = ((x >>> 1) + x) + 5

    If x is 1, x >>> 1 is 0, not 0.5 because you’ve just gone off the bottom of the word.

    output_value = ((1 >>> 1) + 1) + 5 = 0 + 1 + 5 = 6

    There’s nothing special about verilog here. This is true for the majority of languages.

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