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Editorial Team
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Asked: 2026-05-14T18:43:21+00:00

I read the following statement: The x86 architecture includes a specific segment type called

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I read the following statement:

The x86 architecture includes a
specific segment type called the Task
State Segment (TSS), to store hardware
contexts. Although Linux doesn’t use
hardware context switches, it is
nonetheless forced to set up a TSS for
each distinct CPU in the system.

I am wondering:

  • Why doesn’t Linux use the hardware support for context switch?
  • Isn’t the hardware approach much faster than the software approach?
  • Is there any OS which does take advantage of the hardware context switch? Does windows use it?

At last and as always, thanks for your patience and reply.

———–Added————–

http://wiki.osdev.org/Context_Switching got some explanation.

People as confused as me could take a look at it. 8^)

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1 Answer

  1. Editorial Team

    The x86 TSS is very slow for hardware multitasking and offers almost no benefits when compared to software task switching. (In fact, I think doing it manually beats the TSS a lot of times)

    The TSS is known also for being annoying and tedious to work with and it is not portable, even to x86-64. Linux aims at working on multiple architectures so they probably opted to use software task switching because it can be written in a machine independent way. Also, Software task switching provides a lot more power over what can be done and is generally easier to setup than the TSS is.

    I believe Windows 3.1 used the TSS, but at least the NT >5 kernel does not. I do not know of any Unix-like OS that uses the TSS.

    Do note that the TSS is mandatory. The thing that OSs do though is create a single TSS entry(per processor) and everytime they need to switch tasks, they just change out this single TSS. And also the only fields used in the TSS by software task switching is ESP0 and SS0. This is used to get to ring 0 from ring 3 code for interrupts. Without a TSS, there would be no known Ring 0 stack which would of course lead to a GPF and eventually triple fault.

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