Question

I tried to build two programs with one GNU Makefile by either make prog1 or make prog2. I tried to use target-specific variables to specify the source files that are exclusive to the target but test1.c nor test2.c have been build. They’re only referenced on linking the executable. How to get the Makefile to compile either test1.c or test2.c?

Here are the excerpts from my Makefile:

...
prog1: PASRC = test1.c
prog2: PASRC = test2.c
...
ASRC = $(PASRC) common.c
...
OBJS = $(ASRC:.c=.o)
...
prog1: $(OBJS) prog1.elf
prog2: $(OBJS) prog2.elf
...
%elf: $(OBJS)
    $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@

Thanks in advance for your help

Answer 1

There is no need to use target specific variables. Regular dependencies should be enough:

all : prog1 prog2 # default target

prog1 : test1.o 
prog2 : test2.o 
prog1 prog2 : common.o

%.o : %.c # how to build any .o from a corresponding .c
    $(CC) -c -o $@ $(CPPFLAGS) $(CFLAGS) $< 

prog1 prog2 : % : 
    $(CC) $^ $(LDFLAGS) $(LDLIBS) -o $@