Question

I try to implement a non-recursive make build system in my current project. What I struggle with is variables scopes. Target specific variables don’t fit my needs as often variables define targets and not prerequisites.
What I need is:

Makefile1:

SOMEVAR := original_value
include Makefile2
$(warning $(SOMEVAR))

Makefile2:

#some magic here to do what I want and make me happy
SOMEVAR := included_value
#and maybe here

And the output I want is ‘original_value’.

Are there any strategies to make it real?

EDIT: The only solution I came for the moment is to force and organize myself to place all inlcudes in the end of each particular Makefile and use immediate variable assignment :=

Answer 1

One strategy is the old-fashioned solution to variable name collisions when all you have is global variables: add a prefix to your variable names in a form of poor-man’s namespaces.

Makefile1:

Makefile1_SOMEVAR := original_value
include Makefile2
$(warning $(Makefile1_SOMEVAR))

Makefile2:

# no magic needed
Makefile2_SOMEVAR := included_value
# rest of Makefile2 uses $(Makefile2_SOMEVAR) of course

Hey presto, with a convention like this it’s as if each makefile has its own local variables (or, at least, its own variables in a namespace that doesn’t collide with any other makefiles).