Question

i use alias command in vhdl but had error “Index constraint cannot be applied to already-constrained type vec.”

my code is

    type vec is array (11 downto 0) of std_logic;
    signal s:vec;
    alias s1:vec (3 downto 0) is s(11 downto 8);
    alias s2:vec (4 downto 0) is s(7 downto  4);

Answer 1

This will do:

signal vec: std_logic_vector(11 downto 0);-- std_logic_vector IS an array of std_logic's
alias s1: std_logic_vector(3 downto 0) is vec(3 downto 0);
alias s2: std_logic_vector(3 downto 0) is vec(7 downto 0);-- note: Left: #4 = Right: #4