I want to call a makefile by passing the environment variable CPU_TYPE and its value -mcpu=603 as command line argument to that makefile. I am entering the below command
make -f make_file CPU_TYPE=-mcpu=603
But its given error because environment variable value is having = symbol. How to escape this equal symbol in the environment value.
Note : I cant add this environment variable or any other variable inside make_file. I have to pass it as command line arugments only.
Improbable possibility
There shouldn’t be any problem, but maybe you are running afoul of a seldom-used shell feature.
If you use
set -kin a running shell, or usesh -kto run a shell, it will treat anything that looks like an environment variable as an environment variable.You probably already know that shells other than the C shell family can set an environment variable for a single command by adding it before the command:
The command itself sees the modified environment; the shell’s search for
cmdnameis not altered. However, withset -kin effect, anything that looks like an environment variable is treated as one:You can validate this by using
env, for example, as the command. There are sound reasons (such as theddcommand) for not making this the default behaviour.Against the hypothesis
Against this hypothesis, I don’t know of a shell that objects to the ‘
=‘ in the environment value. It would be a nuisance if there was such a restriction.Plain GNU Make is OK
However, I’m able to do:
and, with
set -kin effect, I can also do:In both cases, the compilation takes the value specified via the command line as overriding what is set in the makefile.
The single quotes aren’t seen by
make; they are removed by the shell, of course. You can perfectly well omit them and I get the same result. I’m running usingbashon MacOS X, but I’d expect the same results on any Unix-like system using any of the standard POSIX-ish shells (Bourne, Korn, Bash).