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Home/ Questions/Q 6748371
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Editorial Team
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Editorial Team
Asked: May 26, 20262026-05-26T12:33:25+00:00 2026-05-26T12:33:25+00:00

I want to call a makefile by passing the environment variable CPU_TYPE and its

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I want to call a makefile by passing the environment variable CPU_TYPE and its value -mcpu=603 as command line argument to that makefile. I am entering the below command

make -f make_file CPU_TYPE=-mcpu=603

But its given error because environment variable value is having = symbol. How to escape this equal symbol in the environment value.

Note : I cant add this environment variable or any other variable inside make_file. I have to pass it as command line arugments only.

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  1. Editorial Team
    Editorial Team
    2026-05-26T12:33:26+00:00Added an answer on May 26, 2026 at 12:33 pm

    Improbable possibility

    There shouldn’t be any problem, but maybe you are running afoul of a seldom-used shell feature.

    If you use set -k in a running shell, or use sh -k to run a shell, it will treat anything that looks like an environment variable as an environment variable.

    You probably already know that shells other than the C shell family can set an environment variable for a single command by adding it before the command:

    PATH="/somewhere/else:$PATH" cmdname -opts file1 file2
    

    The command itself sees the modified environment; the shell’s search for cmdname is not altered. However, with set -k in effect, anything that looks like an environment variable is treated as one:

    cmdname -opts PATH="/somewhere/else:$PATH" file1 file2
    

    You can validate this by using env, for example, as the command. There are sound reasons (such as the dd command) for not making this the default behaviour.

    Against the hypothesis

    Against this hypothesis, I don’t know of a shell that objects to the ‘=‘ in the environment value. It would be a nuisance if there was such a restriction.

    Plain GNU Make is OK

    However, I’m able to do:

    make CFLAGS='-Dxyz=pqr' progname
    

    and, with set -k in effect, I can also do:

    make -e CFLAGS='-Dxyz=pqr' progname
    

    In both cases, the compilation takes the value specified via the command line as overriding what is set in the makefile.

    The single quotes aren’t seen by make; they are removed by the shell, of course. You can perfectly well omit them and I get the same result. I’m running using bash on MacOS X, but I’d expect the same results on any Unix-like system using any of the standard POSIX-ish shells (Bourne, Korn, Bash).

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