Question

I want to have a neat makefile containing explicit dependencies but placing all .o objects in a separate directory to link it altogether later (in an another file).

The problem is that my make stops after compiling the first source and then stops with no error whatsoever.

CC=gcc
CFLAGS=-c -Wall -pedantic -std=c99

DIR=../obj

$(DIR)/CList.o : CList.c CList.h CList_aux.h Observation.h CList_View_aux.h
    $(CC) $(CFLAGS) CList.c -o $@
$(DIR)/CList_aux.o : CList_aux.c CList.h CNode.h
    $(CC) $(CFLAGS) CList_aux.c -o $@
$(DIR)/CList_View_aux.o : CList_View_aux.c CNode.h Observation.h
    $(CC) $(CFLAGS) CList_View_aux.c -o $@
$(DIR)/CNode.o : CNode.c CNode.h CNode_aux.h Observation.h CList.h
    $(CC) $(CFLAGS) CNode.c -o $@
$(DIR)/CNode_aux.o : CNode_aux.c CNode.h Observation.h
    $(CC) $(CFLAGS) CNode_aux.c -o $@
$(DIR)/Observation.o : Observation.c Observation.h Observation_aux.h CNode.h
    $(CC) $(CFLAGS) Observation.c -o $@
$(DIR)/Observation_aux.o : Observation.c Observation.h
    $(CC) $(CFLAGS) Observation_aux.c -o $@
$(DIR)/Record.o : Record.c Record.h Observation.h
    $(CC) $(CFLAGS) Record.c -o $@

Answer 1

By default, make builds the first target in the makefile. In this case, that is ${DIR}/CList.o.

You need a different first target, conventionally called all:

OBJECTS = \
    $(DIR)/CList.o \
    $(DIR)/CList_aux.o \
    $(DIR)/CList_View_aux.o \
    $(DIR)/CNode.o \
    $(DIR)/CNode_aux.o \
    $(DIR)/Observation.o \
    $(DIR)/Observation_aux.o

all: ${OBJECTS}

Note that this works whether there are any object files in the ${DIR} or not; a wildcard looking for object files in the directory makes sure that those that have already been compiled once are up to date, but doesn’t try building those which failed to compile previously, or simply aren’t there.