Question

I want to specify some command line parameters in a makefile. I normally run my program like
this:

 gcc -o prog prog2.c prog.c

 ./prog text1.txt text2.txt

Makefile:

prog: prog2.o prog.o
    gcc -o prog prog2.o prog.o 


prog2.o: prog2.c prog2.h
    gcc -c prog2.c

clean :
    rm prog2.o

How do I include the txt files here?

Also how do I give executions in a single make file. Say if I also want to run

  gcc -o prog prog3.c prog.c

  ./prog text1.txt text2.txt

Answer 1

Make a run target:

.PHONY: run
run: prog
    ./prog text1.txt text2.txt

prog: prog2.o prog.o
    gcc -o prog prog2.o prog.o

# etc.

Then you can say make run, or just make if run is the first target in the Makefile.