Question

I want to write a lot of tiny example programmes for one same library, each needs gcc $(OtherOpt) -o xxx -lthelibname xxx.c.

How to write a Makefile without dozens of tagret lines ?

Answer 1

Pattern rules are your friend for these situations. As long as your targets all match a predictable pattern — and they do in this case, as they are all of the form “create foo from foo.c” — you can write a single pattern rule that will be used for all of the targets:

OtherOpt=-Wall -g
all: $(patsubst %.c,%,$(wildcard *.c))
%: %.c
        gcc $(OtherOpt) -o $@ -lthelibname $<

Now you can either run simply make to build all your apps, or make appname to build a specific app. Here I’ve created a single pattern rule that will be used anytime you want to create something from something.c. I used the $@ automatic variable, which will expand to the name of the output, and the $< variable, which will expand to the name of the first prerequisite, so that the command-line is correct regardless of the specific app being built. Technically you don’t need the all line, but I figured you probably didn’t want to always have to type in the name(s) of the apps you want to build.

Also, technically you can probably get away without having any of this makefile, because GNU make already has a built-in pattern rule for the %: %.c relationship! I mention this option only for completeness; personally, I prefer doing things the way I’ve shown here because it’s a little bit more explicit what’s going on.