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I was able to put together bits here and there about the Sandy Bridge-E architecture but I am not totally sure about all the parameters e.g. the size of the L2 cache. Can anyone please confirm they are all correct? My main source was the 64-ia-32-architectures-optimization-manual.pdf
On sandy bridge, each core has 256KB of L2 (see the datasheet, section 1.1). for 6 cores, that’s 1.5MB, but since each core only accesses its own, it’s better to always look at it as 256KB per core.
Moreover, the peak gflops looks completely wrong. AVX is 16 flops/cycle (as single floats). with 6 cores, that’s ~307 gflops/s at 3.2GHz.
Most of the rest of the data looks ok (looking at the datasheet and the specification of that model in particular), though I don’t know for sure the associativity of each cache.