Question

I was asked this question in a job interview recently. I answered that I wud use a hash data structure to begin with designing the system. But couldn’t answer that well. I think the interviewer was looking for answers like how will i design a page table for this.

I would like to know how to answer this question. Like for each page size being 4K how many pages would be needed for 1Gb? Also, what other considerations I should keep in my mind to design it efficiently.

Answer 1

This question makes sense in the context of CPUs where the TLBs are
“manually” loaded and there are no predetermined page table
structures, like some models of MIPS, ARM, PowerPC.

So, some rough thoughts:

1G is 2^30 bytes or 2^18 = 256K 4K pages

Say, 4-byte entry per page, that’s 1M for a single level page
table. Fast, but a bit wasteful on memory.

What can we do to reduce memory and still make it reasonably fast.

We need 18 bits per page frame number, cannot squeeze it in 2 bytes,
but can use 3-bytes per PTE, with 6 bits to spare to encode – access
rights, presence, COW, etc. That’s 768K.

Instead of the whole page frame number we can keep only 16-bits of it,
with the remaining two determined by a 4-entry upper level page table
with a format like this:

• 2 MSB of the physical page number
• 21 bits for second level page table (30 bit address, aligned on 512K
  boundary)
• spare bits

No place for per-page bits though, so lets move a few more address
bits to the upper level table to obtain

Second level page table entry (4K 2-byte entries = 8K)

• 4 bits for random flags
• 12 LSB of the page frame address

First level page table entry format (64 4-byte entries = 256 bytes):

• 6 MSB of the page frame address
• 17 bits for second level page table address (30-bit address aligned
  at 8K)
• spare bits