Question

I wish to resize an entity port after a generic parameter in VHDL.

Here’s my entity declaration :

library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
use ieee.numeric_std.all;

entity counter is
generic( 
    ticks   : natural := 10
);
port(
        clk : in  std_logic;
        f_v : in std_logic_vector(natural(FLOOR(LOG2(Real(ticks)))) downto 0); --forced value
        res : in std_logic;
          z : out std_logic_vector(natural(FLOOR(LOG2(Real(ticks)))) downto 0)
);
end counter;

More specificly, I want to size f_v and z after the function nest natural(FLOOR(LOG2(Real(ticks)))) when instantiating a counter entity.

The code compiles, but when I try to generate a symbol file, I got the following error messages :

Error (10017): Can't create symbol/include/instantiation/component file for entity "counter" because port "f_v" has an unsupported type    

Error (10017): Can't create symbol/include/instantiation/component file for entity "counter" because port "z" has an unsupported type

I am using Altera Quartus II 9.1 Web Edition.

How can I get this working?

Answer 1

This works for me using Quartus II 12.1 (full version). You should know right up front that when it comes to VHDL, there’s a difference between code that is valid and appears to be synthesizable, and code that your synthesis tool can actually understand. Such problems happen a lot with older tools and when you try to do something in a non-standard way or use features of the language that are not commonly used. In your case the tool is most likely having problems with the real type. I would recommend either:

1. Upgrading to the newest version of Quartus II
2. Passing the width of the ports as a generic instead
3. Using your own log2 function from a library (this is what I do.)