Question

I would like to build a rule like this one in my Makefile:

log: test_A test_B
    ./test_A >> $@
    ./test_B >> $@

but test_A and test_B are part of a $(TESTS) variable.

So, is it possible to do an action (here: call the program) for each prerequisite in GNU/make?

Note: How do I make a makefile rule execute its prerequisites? does not completely solve this problem, as the target log is required (make log).

Answer 1

Essentially you want to loop over the prerequisites. The obvious way to do this is to punt to the shell:

log: test_A test_B
        for f in $^; do ./$$f; done

Or you could write the loop as a GNU Make foreach loop, though you have to be careful that the commands that result from the body of the loop appear on separate lines (via define) or are terminated with a shell terminator (i.e., a semi-colon, which is easier):

log: test_A test_B
        $(foreach f,$^,./$(f);)

Finally, in this case you could write it more succinctly and more obscurely as a pattern substitution on each item to be looped over:

log: test_A test_B
        $(patsubst %,./%;,$^)

(I’m sure you can add the output redirection and $(TESTS) variable as appropriate.)