Question

I would like to cross-compile a simple program for ARM architecture using the arm-linux-gcc suite of compilers [arm-linux-gcc (Buildroot 2011.08) 4.3.6]. I’ve attempted to use a simple makefile for compiling C code, and another simple makefile for compiling C++ code. For example, my makefile for C code is reproduced below, but it does not create an ELF binary for running on my embedded system. The host system is x64 GNU Linux.

Here is the listing of my very simple makefile for a C program:

CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o 

clean:
    rm -f test test.o 

The makefile reproduced above only creates an object file with extension .o, and does not create an ELF binary.

I’ve Googled for a good solution, but I can’t seem to find one webpage showing example cross-compile ARM makefiles for both C and C++ programs. Perhaps an answer to this post could show such examples.

Answer 1

I tried your Makefile and changed the following:

test: test.o

It worked after this changed and created a binary called test. It seems that there is some implicit rule that knows how to link whatever if one of its dependencies is whatever.o.

Another way is to list the rule explicitly:

main: test.o
        $(CC) -o $@ $$

This uses the special macros $@ (which means target) and $$ (which means dependencies).