Question

I would like to have a makefile like this:

cudaLib :
    # Create shared library with nvcc

ocelotLib :
    # Create shared library for gpuocelot

build-cuda : cudaLib
    make build

build-ocelot : ocelotLib
    make build

build :
    # build and link with the shared library

I.e. the *Lib tasks create a library that runs cuda directly on the device, or on gpuocelot respectively.

For both build tasks I need to run the same build steps, only creating the library differs.

Is there an alternative to running make directly?

make build

Kind of a post-requisite?

Answer 1

As you have written it, the build target will need to do something different depending on whether you have just done an ocelot or cuda build. That’s another way of saying you have to parameterise build in some way. I suggest separate build targets (much like you already have), with associated variables. Something like:

build-cuda: cudaLib
build-ocelot: ocelotLib

build-cuda build-ocelot:
    shell commands
    which invoke ${opts-$@}

On the command-line you type make build-cuda (say). Make first builds cudaLib, then it carries out the recipe for build-cuda. It expands the macros before calling the shell. $@ in this case is build-cuda, thus ${opts-$@} is first expanded to ${opts-build-cuda}. Make now goes on to expand ${opts-build-cuda}. You will have defined opts-build-cuda (and of course its sister opts-build-ocelot) elsewhere in the makefile.

P.S. Since build-cuda et. al. are not real files, you had better tell make this (.PHONY: build-cuda).