Question

I would like to know your opinion on how to test and manage input signals of a component that are ‘U’, ‘X’, ‘-‘, …

For example, if I want the output to be ‘X’ for all non-valid inputs, where at least one bit of the input isn’t ‘0’ or ‘1’:

entity foo is
    port (
        signal inp : std_logic_vector(7 downto 0);
        signal outp: std_logic );
end entity foo;

architecture bar of foo is
begin
    process(inp)
        if (inp < "11001010") then
            outp <= '1';
        else
            outp <= '0';
        end if;
    end process;
end architecture bar;

This way, the test defaults to being false.

How would be a general way to test the inputs?

Answer 1

Use Is_X from std_logic_1164; it will return true if your std_logic_vector contains any of ‘U’, ‘X’, ‘Z’, ‘W’, ‘-‘.

Is_X will always return false during synthesis (you can e.g. use Is_X('W') to test whether you’re in simulation or synthesis.)