Question

I would like to probe a tristate signal using chipscope.

According to this answer record, it can’t be done, so this is what I started with (only relevant code included):

-- Tristate signals
FPGA_SMB0_SDA <= sysmon_iic_data;
FPGA_SMB0_SCL <= sysmon_iic_clk;

-- Output signals
DEBUG_LED0 <= '0';  
DEBUG_LED1 <= '0';   

Which builds fine with no errors.

Attempt 1:

This is my first attempt at generating a debug signal for probing that’s just an out:

-- Tristate signals
FPGA_SMB0_SDA <= sysmon_iic_data;
FPGA_SMB0_SCL <= sysmon_iic_clk;

-- Generating new output signals using tristate (tristate signals are either '0' or 'X' for IIC)
sysmon_iic_data_debug <= '0' when (sysmon_iic_data  = '0') else '1'; 
sysmon_iic_clk_debug <= '0' when (sysmon_iic_clk  = '0') else '1';   

-- connecting debug outs to debug leds (so that the debug signals aren't optimized out)
DEBUG_LED0 <= sysmon_iic_data_debug;  
DEBUG_LED1 <= sysmon_iic_clk_debug;   

The above code passes synthesis but NGDbuild gives the following errors:

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS25 ;>
   [frm121401u1r1.ucf(333)]: NET "FPGA_SMB0_SDA"
   not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

The above is repeated 8 times, twice for each net.

Attempt 2:

Second thing I tried was using a process:

FPGA_SMB0_SDA <= sysmon_iic_data;
FPGA_SMB0_SCL <= sysmon_iic_clk;

gen_sysmon_debug : process(refclk_10m,refclk_10m_rst)
begin
    if (refclk_10m_rst = '1') then
        sysmon_iic_data_debug <= '0';
        sysmon_iic_clk_debug <= '0';
    elsif (rising_edge(refclk_10m)) then
        if (sysmon_iic_clk = '0') then
            sysmon_iic_clk_debug <= '0';
        else
            sysmon_iic_clk_debug <= '1';            
        end if;
        if (sysmon_iic_data = '0') then
            sysmon_iic_data_debug <= '0';
        else
            sysmon_iic_data_debug <= '1';       
        end if;

    end if;
end process;

DEBUG_LED0 <= sysmon_iic_data_debug;  
DEBUG_LED1 <= sysmon_iic_clk_debug;   

That gave me this NGDbuild error:

ERROR:NgdBuild:924 - bidirect pad net 'FPGA_SMB0_SDA' is driving non-buffer primitives:
     pin D on block sysmon_iic_data with type FDC,

Two of those, one for SDA and one for SCL

More Info:

This is what’s in my UCF:

NET "DEBUG_LED0" LOC = "AK33" | IOSTANDARD = LVCMOS25 ;
NET "DEBUG_LED1" LOC = "AK34" | IOSTANDARD = LVCMOS25 ;
...
NET "FPGA_SMB0_SCL" LOC = "G13" | IOSTANDARD = LVCMOS25 ;
NET "FPGA_SMB0_SDA" LOC = "H13" | IOSTANDARD = LVCMOS25 ;

And top-level vhdl net definitions:

DEBUG_LED0 : out std_logic;
DEBUG_LED1 : out std_logic;

FPGA_SMB0_SCL : inout std_logic;
FPGA_SMB0_SDA : inout std_logic;

and in uBlaze .mhs:

PORT xps_iic_1_Sda_pin = xps_iic_1_Sda, DIR = IO, BUFFER_TYPE = NONE
PORT xps_iic_1_Scl_pin = xps_iic_1_Scl, DIR = IO, BUFFER_TYPE = NONE

I’m completely at a loss why I’m getting these NGDbuild errors, anyone have any ideas?

Answer 1

Your net is probably getting renamed now you’ve connected another signal to it 🙁

Take the constraints out, let it build.

Load the NCD file into FPGA editor and see what the net ends up being called, and use that in your UCF.

Or instantiate all the IOBs yourself in the top level VHDL file, then you know the nae of the net between the IOB “pin” and the real pin won’t change and you can constrain that net.