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I’d like to generate pseudo-random ARM instructions. Via assembler directives, I can tell gcc what mode I’m in, and it will complain if I try a set of opcodes and operands that’s not legal in that mode, so it must have some internal listing of what can be done in which mode. Where does that live? Would it be easier to extract that info from LLVM?
Is this question “not even wrong”? Should I try a different approach entirely?
To answer my own question, this is actually really easy to do from arm.md and and constraints.md in gcc/config/arm/. I probably spent more time answering asking this question and answering comments for it than I did figuring this out. Turns out I just need to look for ‘TARGET_THUMB1’, until I get around to implementing thumb2.