Question

If I have an if statement like:

if(risingEdge && cnt == 3'b111)
begin
  ...
end

Will it check on cnt if risingEdge is not true?

Does this even matter inside of an HDL?

Answer 1

For simulation it is undefined as to whether short-circuited expressions are evaluated or not. In the above example it makes no difference, but if you have a function call on the right hand side then you may run into problems with undefined side effects.

See Gotcha #52 in “Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them” by Stuart Sutherland and Don Mills.