Question

I’m attempting to put together a makefile that will take source files from a directory (eg. src), compile them into object files in another directory (eg. build), and then take those files and create a static library from them in the main directory.

Here’s my effort so far:

LIBNAME := test
LIBNAME := lib$(LIBNAME).a

CC = g++
CFLAGS := -O0 -Wall -g -fPIC
INCLUDE := include
SOURCE := src
BUILD := build

CPPFILES := $(foreach dir, $(SOURCE)/, $(notdir $(wildcard $(SOURCE)/*.cpp)))
OBJFILES := $(addprefix $(BUILD)/, $(CPPFILES:.cpp=.o))

all: $(LIBNAME) $(OBJFILES)

$(LIBNAME): $(OBJFILES)
    ar rcs $(LIBNAME) $(OBJFILES)

.cpp.o:
    $(CC) $(CFLAGS) -I$(INCLUDE) -c $< -o $@

clean:
    rm -rf $(BUILD)

Which gives me this:

make: *** No rule to make target `build/point.o', needed by `libtest.a'.  Stop

Answer 1

You seem do be requiring GNU make anyway (foreach function), so rewriting the old-style suffix rule .cpp.o to

$(BUILD)/%.o : $(SOURCE)/%.cpp

should do the trick. You might also try using the VPATH variable or the vpath directive, see the make manual for these.

In general, you might just tackle this problem with automake, which does most of this stuff for you.