Question

Im doing a homework where I need to write down the value of the control signals for 5 instructions and am trying to figure out the sample first (code at the bottom). The 5 instructions I need to do are

Address    Code        Basic                 Source

0x00400014  0x12120004  beq $16,$18,0x0004    15    beq $s0, $s2, exit
0x00400018  0x8e080000  lw $8,0x0000($16)     16    lw  $t0, ($s0)
0x0040001c  0x02118020  add $16,$16,$17       17    add $s0, $s0, $s1
0x00400020  0xae08fffc  sw $8,0xfffc($16)     18    sw  $t0, -4($s0)
0x00400024  0x08100005  j 0x00400014          19    j   loop

And the example he did is for addi $s1,$0,4 . Right now I have this for it:

    Address    Code       Basic                 Source
    0x00400028 0x20110004 addi $16,$0,4         20 addi     $s1, $0, 4   

where I think the 4 in the basic column is incorrect. What would be the right answer?

Heres the sample he did for that, and below that is the diagram he is referring to with the control signals:

##--------------------------
# Example
# addi  $s1, $0, 4
# Although not supported as in Figure 4.24, the instruction can be easily
# supported with minor changes in the control circuit.

instruction_address=0x00400028 
instruction_encoding=0x20110004

OPcode=0b001000

Jump=0
Branch=0
Jump_address=0x00440010    # not used in this instruction
Branch_address=0x0040003C  # not used in this instruction

Read_register_1=0b00000
Read_register_2=0b10001
Sign_extend_output=0x00000004 

ALUSrc=1            # pick the value from sign_extend_output
ALUOp=0b00          # assume the same value as load/store instruction
ALU_control_input=0b0010    # add operation, as in load/store instruction

MemRead=0
MemWrite=0
MemtoReg=0          # select the ALU result 

RegDst=0
Write_register=0b10001      #register number for $s1
RegWrite=1

##--------------------------

Answer 1

Lets examine the breakdown of the first instruction: beq $s0, $s2, exit.

The instruction address is given under the address column above: 0x00400014. You have the encoding as well: 0x12120004. The encoding is the machine instruction. Lets represent the instruction in binary: 000100 10000 10010 0000000000000100.

This is an I-type instruction. The first group of six bits is the opcode, the second group of five is the source register, the third group of five is the temporary register, and the last group of sixteen is the immediate value.

The opcode is then 0b000100. Since this is an I-type instruction, we aren’t jumping to a target, thus the Jump signal is 0. However, we are branching, so the Branch signal is 1.

To find the Jump_Address, even though it is ignored, examine the the least significant 26 bits: 10000 10010 0000000000000100. Since addresses are word-aligned, we can enlarge the range of reachable addresses by having the jump offsets be the signed difference between the next instruction and target address. In other words, if my target address is 8 bytes away from the next instruction (PC-relative addressing), I’ll use 2 to represent the offset. And this is why we must shift the offset 2 bits to the left. So we end up with Jump_Address = 10 00010 01000 0000000000010000 or 0x8480010.

To find the Branch_Address, which will be used, examine the least significant 16 bits: 0000000000000100. That’s sign extended and shifted 2 bits to the left to get: 0000000000000000 0000000000010000 or 0x00000010. This immediate value will be added to the program counter, which points to the next instruction: 0x00400018. So we finally end with Branch_Address = 0x00400028. I’m assuming the exit label points to the next instruction after the five you’ve posted above, right after the j instruction.

The registers are straightforward. Read_register_1 = 0b10000 and Read_register_2 = 0b10010.

The Sign_extend_output is just the immediate field sign-extended: 0x00000004.

On to the ALU control signals. ALUSrc controls the multiplexer between the register file and ALU. Since a beq instruction requires the use of two registers, we need to select the Read data 2 register from the register file. We aren’t using the immediate field for an ALU computation, like with the addi instruction. Therefore, the ALUSrc is 0.

The ALUOp and ALU_control_input are hard-wired values that are created from the opcode. ALUOp = 0b01 and ALU_control_input = 0b0110. Pg. 323 of Computer Organization and Design, 4th. Edition Revised by Hennessey and Patterson and this web page have a table with the appropriate control signals for a beq instruction. Pg. 318 has a table with the ALU control bit mappings.

MemRead and MemWrite are 0 since we aren’t accessing memory; MemToReg is X (don’t care) since MemWrite is 0; RegWrite is 0 since we aren’t writing to the register file; RegDst is X since RegWrite is 0; and lastly, to find Write_register, take bits 16-20 (look at the multiplexer between the instruction memory and register file), which are 0b10010.