Question

I’m learning about Makefiles and application cross-compiling, and I’d like to find a way to prevent variables from being redefined in Makefiles further down the chain.

As an example, I write a top-level Makefile /usr/src/someapp.mk that will…

1) download the application’s source code from the web into /usr/src/someapp-1.2.3/

2) untar the source, and

3) run its original /usr/src/someapp-1.2.3/Makefile

Since the original Makefile was written as a stand-alone script, it will unknowningly (re)define the usual suspects (CC, AR/RANLIB, etc.) with local values, effectively erasing the value I chose in the top-level Makefile:

#My top-level /usr/src/someapp.mk:
all:
    wget someapp-1.2.3.tar.gz
    tar xzvf someapp-1.2.3.tar.gz
    cd someapp-1.2.3 && $(MAKE)

#Original Makefile from www /usr/src/someapp-1.2.3/Makefile:
#RANLIB locally redefined... :-/
RANLIB=ranlib

all:
    $(RANLIB)...

I’d like users to be able to download the original source code instead of providing my own, modified version: Is there a way to have “make” either ignore when variables are redefined locally or rewrite them on the fly?

Thank you.

Answer 1

The ?= operator will only define a variable if it is unset.

VAR ?= value

By far the most useful way though is to define variables on the make command line. Such variables become read-only for the duration of the make.

$ cat Makefile
VAR := hello
$(error [${VAR}])

then

$ make
Makefile:2: *** [hello].  Stop.

but

$ make VAR='value overridden'
Makefile:2: *** [value overridden].  Stop.

This suggests your snippet cd someapp-1.2.3 && $(MAKE) becomes $(MAKE) -C someapp-1.2.3 RANLIB=myval.