Home/ Questions/Q 1109059
In Process

The Archive Base Latest Questions

Editorial Team
  • 0
Asked: 2026-05-17T02:10:34+00:00

I’m not in a position to make out the difference between vld4_f32 and vld4q_f32

  • 0

I’m not in a position to make out the difference between vld4_f32 and vld4q_f32 in ARM NEON instructions.

The confusion started when I raised my coding levels and started looking at the assembly instructions rather than the less informative intrinsics.

The reason I need to use vld4 variant instruction here is because, I would like to capture 4 float32_t‘s from every 4th position of my large array.

alt text

The vld4_f32 intrinsics and the corresponding assembly instructions look like this (From this link)

float32x2x4_t vld4_f32 (const float32_t *) 
Form of expected instruction(s): vld4.32 {d0, d1, d2, d3}, [r0]

The vld4q_f32 intrinsics and its corresponding assembly instructions looks like this

float32x4x4_t vld4q_f32 (const float32_t *) 
Form of expected instruction(s): vld4.32 {d0, d1, d2, d3}, [r0]

Well, at the intrinsics level the difference I see is the return type, but if I look at the assembly instruction and the number of registers, they both look like the same. How will the compiler or the assembler know the difference between the two?

Can somebody clarify more on this and also explain how I can achieve loading 4 float32_t values which are positioned at every 4th memory location into a single register?

Share

Leave an answer

You must login to add an answer.

Need An Account,

1 Answer

  1. Editorial Team

    Yes, I found out the difference. I used CodeSourcery to see the actual register contents for all the load instructions. The link I have posted doesn’t give the complete details on the vld4q_f32.

    Okay, first comes the vld4_f32, this loads 4 d registers (e.g. d16-19) each d register is 64 bits long, so this instruction will load the first 8 values interleaved with an interval of 4 as shown in the figure below.
    alt text

    In the second case the vld4q_f32, this loads 8 d registers (e.g. d16-23) instead of four. For a reader of this link, it is not at all clear that 8 registers will be loaded. When I looked at the dis-assembled code for a vld4qf32, it was making use of 8 d registers.

    This instruction will indeed do what I was hoping it to do i.e. to load 4 float32_t values which are at the interval of 4 as shown in the figure below.
    alt text

    • 0