Question

I’m reading through and trying to understand some verilog, and sprinkled through is the compiler directive:

// synopsys template

But I do not know what this is or what it does. My Google Fu in researching variations of ‘verilog templates’ has lead to more example verilog code than answers.

I did find this synopsis user guide: http://acms.ucsd.edu/info/documents/dc/syn3.pdf, which on p282 provides some information, the directive seems to affect this variable:

hdlin_auto_save_templates

Controls whether HDL designs containing parameters are read in as templates.
...

It goes on to imply this directive affects “elaboration” (perhaps delaying it? to what end?), which my current understanding is loosely analogous to the code emission step of traditional compilation, when the verilog is converted to an “actual” hardware representation?

I would appreciate an explanation of what templates are / do in Verilog and perhaps a correction on my understanding of ‘elaboration’ in this context – Thanks!

Answer 1

It goes on to imply this directive affects “elaboration” (perhaps delaying it? to what
end?), which my current understanding is loosely analogous to the code
emission step of traditional compilation, when the verilog is
converted to an “actual” hardware representation?

Not really. Elaboration is part of the language specification and is a required step to process a design. Processing Verilog usually requires two distinct steps which the specification describes as parsing and elaboration. SystemVerilog more precisely defines these and calls them compilation and elaboration.

1364-2005:
Elaboration is the process that occurs between parsing and simulation.
It binds modules to module instances, builds the model hierarchy,
computes parameter values, resolves hierarchical names, establishes
net connectivit, and prepares all of this for simulation. With the
addition of generate constructs, the order in which these tasks occur
becomes significant.

Verilog contains some constructs that makes it impossible to completely build a module then ‘link’ it to a larger design later. Consider the following code:

module mod1 #(parameter WIDTH = 0) (output [WIDTH:0] port1);

generate
if(WIDTH > 3)
  assign port1 = {WIDTH{1'b1}};
else
  assign port1 = {WIDTH{1'b0}}; 
endgenerate

endmodule

When the above module is read, the parser has no idea what WIDTH will be because the value given can be overridden in the instantiation. This prevents it from resolving the code inside the generate block until the entire Verilog source text is read. It gets more complicated with defparams, forward declarations of functions and hierarchical references.

The command // synopsys template and the term ‘templates’ are not part of verilog. Given toolic’s answer and the doc you linked, it appears to tell the tool that any module read after the command will need a parameter definition so it should not be elaborated when read. For instance a netlist will not have any parameter overrides in the instantiations so if you want to place an RTL instance in a netlist, you would need to tell the synthesis tool directly what the parameters should be.