I’m relatively new to (GNU) Make, and find it incedibly difficult. I consider switching to SCons, but still, I’d like to understand.
I have a makefile in a folder, that contains subdirectories ./src, ./obj/[release|debug] and ./bin[release|debug]. The makefile should be able to grab the C++ sources in ./src, compile them into object files in the appropriate ./obj directory, and link these object files and put the result in the appropriate ./bin directory. Here is my makefile (edited for simplicity):
CONFIG = release
#CONFIG = debug
OBJS = Container.o
OBJDIR = obj/$(CONFIG)
BINDIR = bin/$(CONFIG)
VPATH = src $(BINDIR)
vpath %.o $(OBJDIR)
.PHONY: release
release: $(OBJS)
$(CXX) $(LXXFLAGS) -o $(BINDIR)/$@ $^
Container.o: Container.cpp Container.hpp
$(CXX) -c $(CXXFLAGS) -o $(OBJDIR)/$@ $<
The first time I run make, the “release” target will search for “Container.o” in the current folder, as well as in $(OBJDIR). Failing to find it, the secong target will be correctly executed, generating the object file in the correct folder. The “release” target will then execute, but the linker will complain that “Container.o” is not found…
The second time I run make, the “release” target will search for “Container.o” and find it in $(OBJDIR). The linker will then execute correctly (the path where “Container.o” has been found is prepended to the filename).
Is there a way to make it work in a single pass? It drives me crazy!
Make does have a long learning curve, and you’re attempting something tricky (and which runs right into one of Make’s big weaknesses, poor wildcard handling). I’m not sure that my answer will help more than confuse, but at least it will solve your specific problem.
If you want to use the
CONFIGapproach, this will do it:But you can do without it (and without the chore of editing the makefile whenever you want to change configurations):