Home/ Questions/Q 809051
In Process

The Archive Base Latest Questions

Editorial Team
  • 0
Asked: 2026-05-15T00:39:51+00:00

I’m thinking about implimenting a 16 bit CPU in VHDL. A simplish CPU. ADD,

  • 0

I’m thinking about implimenting a 16 bit CPU in VHDL.
A simplish CPU.
ADD, MULS, NEG, BitShift, JUMP, Relitive Jump, BREQ, Relitive BREQ, i don’t know somethign along these lines>
Probably all only working with 16bit operands.
I might even cut it down and use only a single operand and a accumulator.
With Some status regitsters, Carry, Zero, Neg (unless i use a Accumlator),

I know how to design all the parts from logic gates, and plan to build them up from first priciples,
So for my ALU I’ll need to ‘build’ a ADDer, proably a Carry Look ahead, group adder,
this adder it self is make up oa a couple of parts, wich are themselves made up of a couple of parts.

Anyway, my problem is not the CPU design, or the VHDL (i know the language, more or less).
It’s how i should keep things organised.
How should I use packages,
How should I name my processes and port maps? (i’ve never seen the benifit of naming the port maps, or processes)

Share

Leave an answer

You must login to add an answer.

Need An Account,

1 Answer

  1. Editorial Team

    Looking at some existing examples wouldn’t hurt. At the level you’re talking about (naming conventions and such) I’ve never really done much different in hardware design than in software.

    As an aside, I’d generally advise against doing things like your own adders and such, unless it’s something that’s required because it’s homework, or something like that. With FPGA’s and (to a slightly lesser extent) ASICs, you have an existing “library” of hardware in the device, so some thing like A <= B + c will typically use an adder circuit that’s already built into the device in the case of an FPGA or a hand-optimized hard macro in the case of an ASIC.

    Writing your own will take a fair amount of extra work, and it’ll almost always produce a worse result. In the case of an ASIC, it’ll be a little worse; in the case of an FPGA, it’ll usually be quite a bit worse.

    Edit: I should also note that a simple CPU doesn’t really qualify as a large-scale design, at least IMO. Maybe it’s due to my background in software, but I’ve always found CPU design fairly straightforward. Just for one example, the one time I did a DRAM controller, it seemed like a lot more work to me. I don’t recall anything like source code line counts, but based on memory, I’d say it was larger (probably by something like 2x). Of course, it’ll depend on exactly how simple of a CPU you decide on too…

    • 0