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Home/ Questions/Q 9322805
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Editorial Team
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Editorial Team
Asked: June 19, 20262026-06-19T04:11:14+00:00 2026-06-19T04:11:14+00:00

I’m trying to clamp a value between -127 and 127 on a Cortex-M based

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I’m trying to clamp a value between -127 and 127 on a Cortex-M based microcontroller.

I have two competing functions, one uses conditionals the other uses a branchless hack I found here.

// Using conditional statements
int clamp(int val) { return ((val > 127) ? 127 : (val < -127) ? -127 : val); }

// Using branchless hacks
int clamp(int val) {
    val -= -127;
    val &= (~val) >> 31;
    val += -127;
    val -= 127;
    val &= val >> 31;
    val += 127;

    return val;
}

Now I know in some cases one of these methods might be faster than the other, and vise-versa but in general is it worth it to use the branchless technique seeing as it doesn’t really matter to me which I use, they both will work just fine in my case?

A little background on the microcontroller, it’s a ARM based microcontroller running at 90 MIPS with a 3 stage pipeline, fetch, decode and execute and it seems to have some sort of branch predictor but I couldn’t dig up details.

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1 Answer

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  1. Editorial Team
    Editorial Team
    2026-06-19T04:11:15+00:00Added an answer on June 19, 2026 at 4:11 am

    ARM code (GCC 4.6.3 with -O3):

    clamp1:
        mvn r3, #126
        cmp r0, r3
        movlt   r0, r3
        cmp r0, #127
        movge   r0, #127
        bx  lr
    
    clamp2:
        add r0, r0, #127
        mvn r3, r0
        and r0, r0, r3, asr #31
        sub r0, r0, #254
        and r0, r0, r0, asr #31
        add r0, r0, #127
        bx  lr
    

    Thumb code:

    clamp1:
        mvn r3, #126
        cmp r0, r3
        it  lt
        movlt   r0, r3
        cmp r0, #127
        it  ge
        movge   r0, #127
        bx  lr
    
    clamp2:
        adds    r0, r0, #127
        mvns    r3, r0
        and r0, r0, r3, asr #31
        subs    r0, r0, #254
        and r0, r0, r0, asr #31
        adds    r0, r0, #127
        bx  lr
    

    Both are branchless thanks to ARM’s conditional execution design. I will bet you they are essentially comparable in performance.

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