Question

I’m trying to create a helloworld module. I have to write a makefile as below.

ifneq ($(KERNELRELEASE), )
obj-m := hello.o
else
KDIR := /path/to/kernel/sources
all:
    make -C  $(KDIR) M= 'pwd' modules
endif

I came to know that this makefile runs twice. How does it run twice by invoking only once?

When is the obj-m value used here?

Answer 1

This makefile has a single rule:

all:
    make -C $(KDIR) M= 'pwd' modules

In English: “go to the directory $(KDIR) and execute Make (the target is modules)”.

So when you invoke Make using this makefile, it invokes Make using another makefile.

You should start with something simpler. We can help, if you tell us what you’re trying to do.