Question

I’m trying to understand how exactly a cache miss occurs. So far this is the way I understand it:
CPU requests for address x, searches its own (L1/L2) cache for it. If it is not there then it’s a cache miss.
Now what is missing here is how exactly does it find out that the information is not available in cache? What information do cache lines reserve? So far I know a cache line should contain this information:

Address of the information, Data within that address.  

Having this information CPU can find out whether an address is available in its cache or not. The problem arises when, it has an invalid copy of data. So my question would be:
How does the processor find out if some data is valid or invalid?
Are there flags stored in each cache line? Does it ask the protocol for this information? If so, where are protocol’s information kept(Cache/Memory/Elsewhere)?
I’m still searching, but I’d appreciate any resources on this.

–EDIT
Similar question asked here, yet no answer. There doesn’t seem to be any detailed information of MESI protocol. Any help is appreciated.

–EDIT2
I found more info in MESI CMP Directory. It states that “L2 cache controller on-chip directory is co-located with the corresponding cache blocks in L2 Cache”, but nothing about where L1 cache controller information resides.

Answer 1

The cache line (L1 or L2) contains the following information:

dirty_bit | many_memory_word

When the dirty bit contains 1 that means the line cache is not similar to the correspondent in the RAM. When it contains 0 that means the line cache contains the exact copy of the memory line actually in the RAM.

When the CPU request an address in the RAM, a translation is made using the MTL to have a correspondent line cache address which is supposed to contain the information.

If there is no address found, that means the information is not on the cache line and then a cache miss happens. If an address on the cache is found, then if the dirty bit of the line requested in the cache is set to 1, a cache miss will happen, and the information actually in the line cache will be written back in memory. The address of the line in the cache makes the CPU know which address corresponds in the real memory RAM.

So when the CPU requesst an information from memory, this information (and more) are put on the line cache, and the dirty bit is set to 0 that means that the cache line represents the exact copy of memory line in the RAM.

Then, when writing operations occur in the line cache, the CPU sets the dirty bit to 1 that means the line does no longer represent the copy actually present in the RAM. So if a reading operation occurs on an address in the cache whose dirty bit is set to 1, a cache miss happens.

Reference: have a look here for more.